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key features single power supply operation ? read, program and erase operations from 2.7 to 3.6 volts ? ideal for battery-powered applications high performance ? 70, 80, 90 and 120 ns access time versions for full voltage range operation ultra-low power consumption (typical/ maximum values) ? automatic sleep/standby current: 0.5/5.0 a ? read current: 9/16 ma (@ 5 mhz) ? program/erase current: 20/30 ma top and bottom boot block versions ? provide one 8 kw, two 4 kw, one 16 kw and sixty-three 32 kw sectors secured sector ? an extra 128-word, factory-lockable sector available for an electronic serial number and/or additional secured data sector protection ? allows locking of a sector or sectors to prevent program or erase operations within that sector ? temporary sector unprotect allows changes in locked sectors fast program and erase times (typicals) ? sector erase time: 0.5 sec per sector ? chip erase time: 32 sec ? word program time: 11 s ? accelerated program time per word: 7 s automatic erase algorithm preprograms and erases any combination of sectors or the entire chip automatic program algorithm writes and verifies data at specified addresses compliant with common flash memory interface (cfi) specification ? flash device parameters stored directly on the device ? allows software driver to identify and use a variety of current and future flash products minimum 100,000 write cycles per sector revision 1.3, may 2002 a[20:0] 21 ce# oe# we# 16 dq[15:0] reset# ry/by# wp#/acc logic diagram compatible with jedec standards ? pinout and software compatible with single-power supply flash devices ? superior inadvertent write protection data# polling and toggle bits ? provide software confirmation of completion of program and erase operations ready/busy (ry/by#) pin ? provides hardware confirmation of completion of program and erase operations write protect function (wp#/acc pin) ? allows hardware protection of the first or last 32 kw of the array, regardless of sector protect status acceleration function (wp#/acc pin) ? provides accelerated program times erase suspend/erase resume ? suspends an erase operation to allow reading data from, or programming data to, a sector that is not being erased ? erase resume can then be invoked to complete suspended erasure hardware reset pin (reset#) resets the device to reading array data space efficient packaging ? 48-pin tsop and 63-ball fbga packages hy29lv320 32 mbit (2m x 16) low voltage flash memory
2 r1.3/may 02 hy29lv320 general description the hy29lv320 is a 32 mbit, 3 volt-only cmos flash memory organized as 2,097,152 (2m) words. the device is available in 48-pin tsop and 63- ball fbga packages. word-wide data (x16) ap- pears on dq[15:0]. the hy29lv320 can be programmed and erased in-system with a single 3 volt v cc supply. inter- nally generated and regulated voltages are pro- vided for program and erase operations, so that the device does not require a higher voltage v pp power supply to perform those functions. the de- vice can also be programmed in standard eprom programmers. access times as fast as 70ns over the full operating voltage range of 2.7 - 3.6 volts are offered for timing compatibility with the zero wait state requirements of high speed micropro- cessors. to eliminate bus contention, the hy29lv320 has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device is compatible with the jedec single- power-supply flash command set standard. com- mands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. device programming is performed a word at a time by executing the four-cycle program command write sequence. this initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. faster program- ming times are achieved by placing the hy29lv320 in the unlock bypass mode, which requires only two write cycles to program data in- stead of four. the hy29lv320 features a sector architecture and is offered in two versions: hy29lv320b - a device with boot-sector archi- tecture with the boot sectors at the bottom of the address range, containing one 8kw, two 4kw, one 16kw and sixty-three 32kw sectors. hy29lv320t - a device with boot-sector archi- tecture with the boot sectors at the top of the address range, containing one 8kw, two 4kw, one 16kw and sixty-three 32kw sectors. the hy29lv320 ? s sector erase architecture allows any number of array sectors to be erased and re- programmed without affecting the data contents of other sectors. device erasure is initiated by executing the erase command sequence. this initiates an internal algorithm that automatically preprograms the array (if it is not already pro- grammed) before executing the erase operation. as during programming cycles, the device auto- matically times the erase pulse widths and veri- fies proper cell margin. sectors are arranged into designated groups for purposes of protection and unprotection. sector group protection optionally disables both program and erase operations in any combination of the sector groups of the memory array, while temporary sector group unprotect allows in-system erasure and code changes in previously protected sector groups. erase sus- pend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for era- sure. true background erase can thus be achieved. the device is fully erased when shipped from the factory. addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the ry/by# pin, or by reading the dq[7] (data# polling) and dq[6] (toggle) status bits. hardware data protection measures include a low v cc detector that automatically inhibits write op- erations during power transitions. after a program or erase cycle has been com- pleted, or after assertion of the reset# pin (which terminates any operation in progress), the device is ready to read data or to accept another com- mand. reading data out of the device is similar to reading from other flash or eprom devices. the secured sector is an extra 128 word sector capable of being permanently locked at the fac- tory or by customers. the secured indicator bit (accessed via the electronic id mode) is perma- nently set to a ? 1 ? if the part is factory locked, and permanently set to a ? 0 ? if customer lockable. this way, customer lockable parts can never be used to replace a factory locked part. factory locked parts provide several options. the secured sec- tor may store a secure, random 8-word esn (elec- tronic serial number), customer code pro- grammed at the factory, or both. customer lock-
3 r1.3/may 02 hy29lv320 block diagram state control we# ce# reset# command register a[20:0] v cc detector timer erase voltage generator and sector switches program voltage generator address latch x-decoder y-decoder 32 mb flash memory array (67 sectors) 128-word flash security sector y-gating data latch i/o buffers i/o control ry/by# dq[15:0] cfi control cfi data memory a[20:0] wp#/acc oe# able parts may utilize the secured sector as bo- nus space, reading and writing like any other flash sector, or may permanently lock their own code there. the wp#/acc pin provides two functions. the write protect function provides a hardware method of protecting the boot sectors without using a high voltage. the accelerate function speeds up pro- gramming operations, and is intended primarily to allow faster manufacturing throughput. two power-saving features are embodied in the hy29lv320. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. the host can also place the device into the standby mode. power con- sumption is greatly reduced in both these modes. common flash memory interface (cfi) to make flash memories interchangeable and to encourage adoption of new flash technologies, major flash memory suppliers developed a flex- ible method of identifying flash memory sizes and configurations in which all necessary flash device parameters are stored directly on the device. parameters stored include memory size, byte/word configuration, sector configuration, necessary volt- ages and timing information. this allows one set of software drivers to identify and use a variety of different, current and future flash products. the standard which details the software interface nec- essary to access the device to identify it and to determine its characteristics is the common flash memory interface (cfi) specification. the hy29lv320 is fully compliant with this specification.
4 r1.3/may 02 hy29lv320 signal descriptions e m a n e p y t n o i t p i r c s e d ] 0 : 0 2 [ as t u p n i . h g i h e v i t c a , s s e r d d a s d r o w ) m 2 ( 2 5 1 , 7 9 0 , 2 f o e n o t c e l e s s t u p n i 1 2 e s e h t . s n o i t a r e p o e t i r w r o d a e r r o f y a r r a e h t n i h t i w ] 0 : 5 1 [ q d s t u p t u o / s t u p n i e t a t s - i r t h g i h e v i t c a , s u b a t a d d n a d a e r r o f h t a p a t a d t i b - 6 1 a e d i v o r p s n i p e s e h t . . s n o i t a r e p o e t i r w # e ct u p n i . w o l e v i t c a , e l b a n e p i h c r o m o r f a t a d d a e r o t d e t r e s s a e b t s u m t u p n i s i h t e h t d n a d e t a t s - i r t s i s u b a t a d e h t , h g i h n e h w . 0 2 3 v l 9 2 y h e h t o t a t a d e t i r w . e d o m y b d n a t s e h t n i d e c a l p s i e c i v e d # e ot u p n i w o l e v i t c a , e l b a n e t u p t u o s n o i t a r e p o d a e r r o f d e t r e s s a e b t s u m t u p n i s i h t . e r a e c i v e d e h t m o r f s t u p t u o a t a d , h g i h n e h w . s n o i t a r e p o e t i r w r o f d e t a g e n d n a . e t a t s e c n a d e p m i h g i h e h t n i d e c a l p e r a s n i p s u b a t a d e h t d n a d e l b a s i d # e wt u p n i . w o l e v i t c a , e l b a n e e t i r w d n a m m o c r o s d n a m m o c f o g n i t i r w s l o r t n o c n e h w e c a l p s e k a t n o i t a r e p o e t i r w a . s n o i t a r e p o e c i v e d s u o i r a v r o f s e c n e u q e s . h g i h s i # e o d n a w o l o s l a s i # e c e l i h w d e t r e s s a s i # e w # t e s e rt u p n i . w o l e v i t c a , t e s e r e r a w d r a h e h t g n i t t e s e r f o d o h t e m e r a w d r a h a s e d i v o r p y l e t a i d e m m i t i , t e s e r s i e c i v e d e h t n e h w . e t a t s y a r r a d a e r e h t o t 0 2 3 v l 9 2 y h e t i r w / d a e r l l a d n a d e t a t s - i r t s i s u b a t a d e h t . s s e r g o r p n i n o i t a r e p o y n a s e t a n i m r e t d e t r e s s a s i # t e s e r e l i h w . d e t r e s s a s i t u p n i e h t e l i h w d e r o n g i e r a s d n a m m o c . e d o m y b d n a t s e h t n i e b l l i w e c i v e d e h t # y b / y r t u p t u o n i a r d n e p o . s u t a t s y s u b / y d a e r n i s i d n a m m o c e s a r e r o e t i r w a r e h t e h w s e t a c i d n i # e w l a n i f e h t f o e g d e g n i s i r e h t r e t f a d i l a v . d e t e l p m o c n e e b s a h r o s s e r g o r p y l e v i t c a s i e c i v e d e h t e l i h w w o l s n i a m e r . e c n e u q e s d n a m m o c a f o e s l u p . a t a d y a r r a d a e r o t y d a e r s i t i n e h w h g i h s e o g d n a , g n i s a r e r o a t a d g n i m m a r g o r p c c a / # p wt u p n i / w o l e v i t c a , t c e t o r p e t i r wv ( e t a r e l e c c a h h . ) v t a n i p s i h t g n i c a l p l i m o t t o b r o p o t e h t n i s n o i t a r e p o e s a r e d n a m a r g o r p s e l b a s i d e h t r o f 3 s - 0 s s r o t c e s e r a s r o t c e s d e t c e f f a e h t . y a r r a e h t f o s d r o w k 2 3 . t 0 2 3 v l 9 2 y h e h t r o f 6 6 s - 3 6 s s r o t c e s d n a b 0 2 3 v l 9 2 y h v t a d e c a l p s i n i p e h t f i h i o t s t r e v e r s r o t c e s o w t e s o h t f o e t a t s n o i t c e t o r p e h t , p u o r g r o t c e s e h t g n i s u d e t c e t o r p n u r o d e t c e t o r p e b o t t e s t s a l e r e w y e h t r e h t e h w . 0 2 3 v l 9 2 y h e h t f o y t i l i b a p a c n o i t c e t o r p n u d n a n o i t c e t o r p v f i h h , e d o m s s a p y b k c o l n u e h t s r e t n e e c i v e d e h t , t u p n i s i h t o t d e i l p p a s i e h t n o e g a t l o v r e h g i h e h t s e s u d n a , s r o t c e s d e t c e t o r p y n a s t c e t o r p n u y l i r a r o p m e t n e h t d l u o w m e t s y s e h t ( . s n o i t a r e p o m a r g o r p r o f d e r i u q e r e m i t e h t e c u d e r o t n i p k c o l n u e h t y b d e r i u q e r s a e c n e u q e s d n a m m o c m a r g o r p e l c y c - o w t e h t e s u v g n i v o m e r ) . e d o m s s a p y b h h l a m r o n o t e c i v e d e h t s n r u t e r n i p e h t m o r f . n o i t a r e p o v t a e b t o n t s u m n i p s i h t h h , g n i m m a r g o r p d e t a r e l e c c a n a h t r e h t o s n o i t a r e p o r o f t l u s e r y a m d e t c e n n o c n u r o g n i t a o l f n i p e h t g n i v a e l . t l u s e r y a m e g a m a d e c i v e d r o . n o i t a r e p o e c i v e d t n e t s i s n o c n i n i v h i t u p n i . t u p n i h g i h v o t t c e n n o c h i v o t r o c c 6 1 x / 8 x r a l i m i s h t i w y t i l i b i t a p m o c e d i v o r p o t . s e c i v e d v c c - - . y l p p u s r e w o p ) l a n i m o n ( t l o v - 3 v s s - - . d n u o r g l a n g i s d n a r e w o p
5 r1.3/may 02 hy29lv320 pin configurations tsop48 a[11] a[10] 5 6 a[9] a[8] 7 8 a[19] a[20] 9 10 we# reset# 11 12 nc wp#/acc 13 14 ry/by# a[18] 15 16 a[17] a[7] 17 18 a[6] a[5] 19 20 a[15] a[14] 1 2 a[13] a[12] 3 4 a[4] a[3] 21 22 a[2] a[1] 23 24 dq[7] dq[14] 44 43 dq[6] dq[13] 42 41 dq[5] dq[12] 40 39 dq[4] v cc 38 37 dq[11] dq[3] 36 35 dq[10] dq[2] 34 33 dq[9] dq[1] 32 31 dq[8] dq[0] 30 29 a[16] v ih 48 47 v ss dq[15] 46 45 oe# v ss 28 27 ce# a[0] 26 25

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6 r1.3/may 02 hy29lv320 conventions unless otherwise noted, a positive logic (active high) convention is assumed throughout this docu- ment, whereby the presence at a pin of a higher, more positive voltage (v ih ) causes assertion of the signal. a ? # ? symbol following the signal name, e.g., reset#, indicates that the signal is asserted in the low state (v il ). see dc specifications for v ih and v il values. whenever a signal is separated into numbered bits, e.g., dq[7], dq[6], ..., dq[0], the family of bits may also be shown collectively, e.g., as dq[7:0]. the designation 0xnnnn (n = 0, 1, 2, . . . , 9, a, . . . , e, f) indicates a number expressed in hexadeci- mal notation. the designation 0bxxxx indicates a number expressed in binary notation (x = 0, 1). memory array organization the 32 mbit flash memory array is organized into 67 blocks called sectors (s0, s1, . . . , s66). a sector or several contiguous sectors are defined as a sector group . a sector is the smallest unit that can be erased and a sector group is the small- est unit that can be protected to prevent acciden- tal or unauthorized erasure. in the hy29lv320, four of the sectors, which com- prise the boot block , are sized as follows: one of eight kwords, two of four kwords and one of sixteen kwords. the remaining 63 sectors are sized at 32 kwords. the boot block can be lo- cated at the bottom of the address range (hy29lv320b) or at the top of the address range (hy29lv320t). tables 1 and 2 define the sector addresses and corresponding array address ranges for the top and bottom boot block versions of the hy29lv320. see tables 6 and 7 for sector group definitions. secured sector flash memory region the secured sector (sec 2 ) feature provides a 128 word flash memory region that enables perma- nent part identification through an electronic se- rial number (esn). an associated ? sec 2 indica- tor ? bit, which is permanently set at the factory and cannot be changed, indicates whether or not the sec 2 is locked when shipped from the factory. the device is offered with the sec 2 either factory locked or customer lockable. the factory-locked version is always protected when shipped from the factory, and has the sec 2 indicator bit perma- nently set to a ? 1 ? . the customer-lockable version is shipped with the sec 2 unprotected, allowing customers to utilize the sector in any manner they choose, and has the sec 2 indicator bit permanently set to a ? 0 ? . thus, the sec 2 indicator bit prevents customer-lockable devices from being used to re- place devices that are factory locked. the bit pre- vents cloning of a factory locked part and thus ensures the security of the esn once the product is shipped to the field. the system accesses the sec 2 through a com- mand sequence (see ? enter/exit secured sector command sequence ? ). after the system has writ- ten the enter secured sector command sequence, it may read the sec 2 by using the addresses speci- fied in table 3. this mode of operation continues until the system issues the exit secured sector command sequence, or until power is removed from the device. on power-up, or following a hard- ware reset, the device reverts to addressing the flash array. note: while in the sec 2 read mode, only the reading of the ? replaced sector ? (table 3) is affected. accesses within the specified sector, but outside the address range specified in the table, may produce indeterminate results. reading of all other sectors in the device continues nor- mally while in this mode. sec 2 programmed and protected at the factory in a factory-locked device, the sec 2 is protected when the device is shipped from the factory and cannot be modified in any way. the device is avail- able preprogrammed with one of the following: a random, secure esn only customer code both a random, secure esn and customer code in devices that have an esn, it will be located at the bottom of the sector: starting at word address 0x000000 and ending at 0x000007 for a bottom boot device, and starting at word address 0x1fe000 and ending at 0x1fe007 for a top boot device. see table 3.
7 r1.3/may 02 hy29lv320 table 1. hy29lv320t (top boot block) memory array organization - t c e s r o e z i s ) d r o w k ( s s e r d d a r o t c e s 1 e g n a r s s e r d d a 3 , 2 ] 0 2 [ a ] 9 1 [ a ] 8 1 [ a ] 7 1 [ a ] 6 1 [ a ] 5 1 [ a ] 4 1 [ a ] 3 1 [ a ] 2 1 [ a 0 s2 3 000000xxx f f f 7 0 0 x 0 - 0 0 0 0 0 0 x 0 1 s2 3 000001xxx f f f f 0 0 x 0 - 0 0 0 8 0 0 x 0 2 s2 3 000010xxx f f f 7 1 0 x 0 - 0 0 0 0 1 0 x 0 3 s2 3 000011xxx f f f f 1 0 x 0 - 0 0 0 8 1 0 x 0 4 s2 3 000100xxx f f f 7 2 0 x 0 - 0 0 0 0 2 0 x 0 5 s2 3 000101xxx f f f f 2 0 x 0 - 0 0 0 8 2 0 x 0 6 s2 3 000110xxx f f f 7 3 0 x 0 - 0 0 0 0 3 0 x 0 7 s2 3 000111xxx f f f f 3 0 x 0 - 0 0 0 8 3 0 x 0 8 s2 3 001000xxx f f f 7 4 0 x 0 - 0 0 0 0 4 0 x 0 9 s2 3 0 0 10 0 1xxx f f f f 4 0 x 0 - 0 0 0 8 4 0 x 0 0 1 s2 3 001010xxx f f f 7 5 0 x 0 - 0 0 0 0 5 0 x 0 1 1 s2 3 001011xxx f f f f 5 0 x 0 - 0 0 0 8 5 0 x 0 2 1 s2 3 0 0 1 10 0xxx f f f 7 6 0 x 0 - 0 0 0 0 6 0 x 0 3 1 s2 3 0 0 1 10 1xxx f f f f 6 0 x 0 - 0 0 0 8 6 0 x 0 4 1 s2 3 001110xxx f f f 7 7 0 x 0 - 0 0 0 0 7 0 x 0 5 1 s2 3 001111xxx f f f f 7 0 x 0 - 0 0 0 8 7 0 x 0 6 1 s2 3 010000xxx f f f 7 8 0 x 0 - 0 0 0 0 8 0 x 0 7 1 s2 3 010001xxx f f f f 8 0 x 0 - 0 0 0 8 8 0 x 0 8 1 s2 3 0 10 0 10xxx f f f 7 9 0 x 0 - 0 0 0 0 9 0 x 0 9 1 s2 3 0 10 0 1 1xxx f f f f 9 0 x 0 - 0 0 0 8 9 0 x 0 0 2 s2 3 0 10 100xxx f f f 7 a 0 x 0 - 0 0 0 0 a 0 x 0 1 2 s2 3 0 10 10 1xxx f f f f a 0 x 0 - 0 0 0 8 a 0 x 0 2 2 s2 3 0 10 1 10xxx f f f 7 b 0 x 0 - 0 0 0 0 b 0 x 0 3 2 s2 3 010111xxx f f f f b 0 x 0 - 0 0 0 8 b 0 x 0 4 2 s2 3 011000xxx f f f 7 c 0 x 0 - 0 0 0 0 c 0 x 0 5 2 s2 3 011001xxx f f f f c 0 x 0 - 0 0 0 8 c 0 x 0 6 2 s2 3 0 1 10 10xxx f f f 7 d 0 x 0 - 0 0 0 0 d 0 x 0 7 2 s2 3 0 1 10 1 1xxx f f f f d 0 x 0 - 0 0 0 8 d 0 x 0 8 2 s2 3 011100xxx f f f 7 e 0 x 0 - 0 0 0 0 e 0 x 0 9 2 s2 3 011101xxx f f f f e 0 x 0 - 0 0 0 8 e 0 x 0 0 3 s2 3 011110xxx f f f 7 f 0 x 0 - 0 0 0 0 f 0 x 0 1 3 s2 3 011111xxx f f f f f 0 x 0 - 0 0 0 8 f 0 x 0 - 2 3 s 2 6 s 2 31 = ] 0 2 [ a t p e c x e 0 3 s - 0 s s a e m a s 0 3 s - 0 s s a e m a s 1 = d s m t p e c x e 3 6 s6 1 1111110xx f f f b f 1 x 0 - 0 0 0 8 f 1 x 0 4 6 s 4 111111100 f f f c f 1 x 0 - 0 0 0 c f 1 x 0 5 6 s 4 111111101 f f f d f 1 x 0 - 0 0 0 d f 1 x 0 6 6 s 8 11111111x f f f f f 1 x 0 - 0 0 0 e f 1 x 0 notes: 1. ? x ? indicates don ? t care. 2. ? 0xn. . . n ? indicates an address in hexadecimal notation. 3. the address range is a[20:0].
8 r1.3/may 02 hy29lv320 table 2. hy29lv320b (bottom boot block) memory array organization notes: 1. ? x ? indicates don ? t care. 2. ? 0xn. . . n ? indicates an address in hexadecimal notation. 3. the address range is a[20:0]. - t c e s r o e z i s ) d r o w k ( s s e r d d a r o t c e s 1 e g n a r s s e r d d a 3 , 2 ] 0 2 [ a ] 9 1 [ a ] 8 1 [ a ] 7 1 [ a ] 6 1 [ a ] 5 1 [ a ] 4 1 [ a ] 3 1 [ a ] 2 1 [ a 0 s8 00000000x f f f 1 0 0 x 0 - 0 0 0 0 0 0 x 0 1 s4 000000010 f f f 2 0 0 x 0 - 0 0 0 2 0 0 x 0 2 s4 000000011 f f f 3 0 0 x 0 - 0 0 0 3 0 0 x 0 3 s6 1 0000001xx f f f 7 0 0 x 0 - 0 0 0 4 0 0 x 0 4 s2 3 000001xxx f f f f 0 0 x 0 - 0 0 0 8 0 0 x 0 5 s2 3 000010xxx f f f 7 1 0 x 0 - 0 0 0 0 1 0 x 0 6 s2 3 000011xxx f f f f 1 0 x 0 - 0 0 0 8 1 0 x 0 7 s2 3 000100xxx f f f 7 2 0 x 0 - 0 0 0 0 2 0 x 0 8 s2 3 000101xxx f f f f 2 0 x 0 - 0 0 0 8 2 0 x 0 9 s2 3 000110xxx f f f 7 3 0 x 0 - 0 0 0 0 3 0 x 0 0 1 s2 3 000111xxx f f f f 3 0 x 0 - 0 0 0 8 3 0 x 0 1 1 s2 3 001000xxx f f f 7 4 0 x 0 - 0 0 0 0 4 0 x 0 2 1 s2 3 0 0 10 0 1xxx f f f f 4 0 x 0 - 0 0 0 8 4 0 x 0 3 1 s2 3 001010xxx f f f 7 5 0 x 0 - 0 0 0 0 5 0 x 0 4 1 s2 3 001011xxx f f f f 5 0 x 0 - 0 0 0 8 5 0 x 0 5 1 s2 3 0 0 1 10 0xxx f f f 7 6 0 x 0 - 0 0 0 0 6 0 x 0 6 1 s2 3 0 0 1 10 1xxx f f f f 6 0 x 0 - 0 0 0 8 6 0 x 0 7 1 s2 3 001110xxx f f f 7 7 0 x 0 - 0 0 0 0 7 0 x 0 8 1 s2 3 001111xxx f f f f 7 0 x 0 - 0 0 0 8 7 0 x 0 9 1 s2 3 010000xxx f f f 7 8 0 x 0 - 0 0 0 0 8 0 x 0 0 2 s2 3 010001xxx f f f f 8 0 x 0 - 0 0 0 8 8 0 x 0 1 2 s2 3 0 10 0 10xxx f f f 7 9 0 x 0 - 0 0 0 0 9 0 x 0 2 2 s2 3 0 10 0 1 1xxx f f f f 9 0 x 0 - 0 0 0 8 9 0 x 0 3 2 s2 3 0 10 100xxx f f f 7 a 0 x 0 - 0 0 0 0 a 0 x 0 4 2 s2 3 0 10 10 1xxx f f f f a 0 x 0 - 0 0 0 8 a 0 x 0 5 2 s2 3 0 10 1 10xxx f f f 7 b 0 x 0 - 0 0 0 0 b 0 x 0 6 2 s2 3 010111xxx f f f f b 0 x 0 - 0 0 0 8 b 0 x 0 7 2 s2 3 011000xxx f f f 7 c 0 x 0 - 0 0 0 0 c 0 x 0 8 2 s2 3 011001xxx f f f f c 0 x 0 - 0 0 0 8 c 0 x 0 9 2 s2 3 0 1 10 10xxx f f f 7 d 0 x 0 - 0 0 0 0 d 0 x 0 0 3 s2 3 0 1 10 1 1xxx f f f f d 0 x 0 - 0 0 0 8 d 0 x 0 1 3 s2 3 011100xxx f f f 7 e 0 x 0 - 0 0 0 0 e 0 x 0 2 3 s2 3 011101xxx f f f f e 0 x 0 - 0 0 0 8 e 0 x 0 3 3 s2 3 011110xxx f f f 7 f 0 x 0 - 0 0 0 0 f 0 x 0 4 3 s2 3 011111xxx f f f f f 0 x 0 - 0 0 0 8 f 0 x 0 5 3 s2 3 100000xxx f f f 7 0 1 x 0 - 0 0 0 0 0 1 x 0 - 6 3 s 6 6 s 2 3 1 = ] 0 2 [ a t p e c x e 4 3 s - 4 s s a e m a s 4 3 s - 4 s s a e m a s 1 = d s m t p e c x e
9 r1.3/may 02 hy29lv320 table 3. hy29lv320 secure sector addressing sec 2 not programmed or protected at the factory if the security feature is not required, the sec 2 can be treated as an additional flash memory space of 128 words. the sec 2 can be read, programmed, and erased as often as required. the sec 2 area can be protected using the following procedure: write the three-cycle enter secure sector re- gion command sequence. follow the in-system sector protect algorithm as shown in figure 3, except that reset# may be at either v ih or v id . this allows in-system pro- tection of the secure sector without raising any device pin to a high voltage. note that this method is only applicable to the secure sector. once the secure sector is locked and verified, the system must write the exit secure sector command sequence to return to reading and writing the remainder of the array. sec 2 protection must be used with caution since, once protected, there is no procedure available for unprotecting the sec 2 area and none of the bits in the sec 2 memory space can be modified in any way. e c i v e d e z i s r o t c e s ) s d r o w ( r o t c e s d e c a l p e r 1 e g n a r s s e r d d a 2 r e b m u n l a i r e s c i n o r t c e l e e g n a r s s e r d d a 2 t 0 2 3 v l 9 2 y h8 2 1) 1 e l b a t ( 6 6 sf 7 0 e f 1 x 0 - 0 0 0 e f 1 x 07 0 0 e f 1 x 0 - 0 0 0 e f 1 x 0 b 0 2 3 v l 9 2 y h8 2 1) 2 e l b a t ( 0 sf 7 0 0 0 0 x 0 - 0 0 0 0 0 0 x 07 0 0 0 0 0 x 0 - 0 0 0 0 0 0 x 0 notes: 1. accesses within the specified sector, but outside the specified address range, may produce indeterminate results. 2. ? 0xn. . . n ? indicates an address in hexadecimal notation. the address range is a[20:0]. bus operations device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. the command register itself does not occupy any addressable memory location. the contents of the command register serve as inputs to an internal state ma- chine whose outputs control the operation of the device. table 4 lists the normal bus operations, the inputs and control levels they require, and the resulting outputs. certain bus operations require a high voltage on one or more device pins. those are described in table 5. data is read from the hy29lv320 by using stan- dard microprocessor read cycles while placing the word address on the device ? s address inputs. the host system must drive the ce# and oe# pins low and drive we# high for a valid read opera- tion to take place. see figure 1. the hy29lv320 is automatically set for reading array data after device power-up and after a hard- ware reset to ensure that no spurious alteration of the memory content occurs during the power tran- sition. no command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register con- tents are altered. this device features an erase suspend mode. while in this mode, the host may read the array data from any sector of memory that is not marked for erasure. if the host reads from an address within an erase-suspended (or erasing) sector, or while the device is performing a program opera- tion, the device outputs status data instead of ar- ray data. after completing an automatic program or erase algorithm within a sector, that sector au- tomatically returns to the read array data mode. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception noted above. the host must issue a hardware reset or the soft- ware reset command to return a sector to the read array data mode if dq[5] goes high during a pro- gram or erase cycle, or to return the device to the read array data mode while it is in the electronic id mode.
10 r1.3/may 02 hy29lv320 table 4. hy29lv320 normal bus operations 1 notes: 1. l = v il , h = v ih , x = don ? t care (l or h), d out = data out, d in = data in. see dc characteristics for voltage levels. 2. if wp#/acc = v il , the boot sectors are protected. if wp#/acc = v ih , the protection state of the boot sectors depends on whether they were last protected or unprotected using the method described in ? sector group protection and unprotection ? . if wp#/acc = v hh , all sectors will be unprotected. 3. see table 5 for accelerated program function with wp#/acc = v hh . n o i t a r e p o # e c # e o # e w # t e s e r c c a / # p w ] 0 : 0 2 [ a ] 0 : 5 1 [ q d d a e rllhhh / la n i d t u o e t i r wlhlh3 , 2 s e t o na n i d n i e l b a s i d t u p t u olhhhh / lx z - h g i h y b d n a t s l a m r o n # e chxxhh / lx z - h g i h y b d n a t s p e e d # e cv c c v 3 . 0 xxv c c v 3 . 0 h / lx z - h g i h ) y b d n a t s l a m r o n ( t e s e r e r a w d r a hxxxlh / lx z - h g i h ) y b d n a t s p e e d ( t e s e r e r a w d r a hxxxv s s v 3 . 0 h / lx z - h g i h table 5. hy29lv320 bus operations requiring high voltage 1, 2 notes: 1. l = v il , h = v ih , x = don ? t care (l or h), v id = 12v nominal. see dc characteristics for voltage specifications. 2. address bits not specified are don ? t care. 3. sa = sector address, sga = sector group address. see tables 1, 2, 6, and 7. a in = address input. 4. if wp#/acc = v il , the boot sectors remain protected. 5. protected sectors are temporarily unprotected when v hh is applied to the wp#/acc pin. 6. normal read, write and output disable operations are used in this mode. see table 4. 7. d in = input data, cmd in = command input. n o i t a r e p o # e c # e o # e w # t e s e r / # p w c c a ] 2 1 : 0 2 [ a 3 ] 9 [ a ] 6 [ a ] 1 [ a ] 0 [ a ] 0 : 5 1 [ q d 7 m a r g o r p d e t a r e l e c c alhlhv h h 5 a n i a n i a n i a n i a n i d m c n i t c e t o r p p u o r g r o t c e slhlv d i ha g sxlhld m c n i t c e t o r p n u r o t c e slhlv d i hxxhhld n i r o t c e s y r a r o p m e t t c e t o r p n u 6 - -- -- -v d i 4 e t o n- -- -- -- -- -- - e d o c r e r u t c a f u n a mllhhh / lxv d i lll d a 0 0 x 0 e c i v e d e d o c b 0 2 3 v l 9 2 y h llh h h / lxv d i llh d 7 2 2 x 0 t 0 2 3 v l 9 2 y h e 7 2 2 x 0 r o t c e s t c e t o r p e t a t s 4 d e t c e t o r p n u llh h h / la sv d i lhl 0 0 x x x 0 d e t c e t o r p 1 0 x x x 0 e r u c e s r o t c e s r o t a c i d n i t i b y r o t c a f d e k c o l llh h h / lxv d i lhh 0 8 x x x 0 y r o t c a f t o n d e k c o l 0 0 x x x 0
11 r1.3/may 02 hy29lv320 we# adr ce# oe# data out t acc t ce t oe figure 1. read operation figure 2. write operation oe# adr ce# we# data in t as t ah t dh t ds we# adr ce# oe# data out t acc t ce t oe figure 1. read operation figure 2. write operation oe# adr ce# we# data in t as t ah t dh t ds write operation certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the hy29lv320. writes to the device are performed by placing the word address on the device ? s ad- dress inputs while the data to be written is input on dq[15:0]. the host system must drive the ce# and we# pins low and drive oe# high for a valid write operation to take place. all addresses are latched on the falling edge of we# or ce#, which- ever happens later. all data is latched on the ris- ing edge of we# or ce#, whichever happens first. see figure 2. .the ? device commands ? section of this specifi- cation provides details on the specific device com- mands implemented in the hy29lv320. accelerated program operation this device offers accelerated program operations through the ? accelerate ? function provided by the wp#/acc pin. this function is intended primarily for faster programming throughput at the factory. if v hh is applied to the wp#/acc input, the device enters the unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time re- quired for program operations. the system would then use the two-cycle program command se- quence as required by the unlock bypass mode. removing v hh from the pin returns the device to normal operation. note: wp# sector protection cannot be used while wp#/ acc = v hh . thus, all sectors are unprotected and can be erased and programmed while in accelerated pro- gramming mode. note: the accelerate function does not affect the time required for erase operations. see the description of the wp#/acc pin in the pin descriptions table for additional information on this function. write protect function the write protect function provides a hardware method of protecting the boot sectors without us- ing v id . this function is a second function pro- vided by the wp#/acc pin. placing this pin at v il disables program and erase operations in the bottom or top 32k words of the array (the boot sectors). the affected sectors are as follows (see tables 1 and 2): hy29lv320b: s0 ? s3 hy29lv320t: s63 ? s66 if the pin is placed at v ih , the protection state of those sectors reverts to whether they were last set to be protected or unprotected using the method described in the sector group protection and unprotection sections. note: sectors protected by wp#/acc = v il remain pro- tected during temporary sector unprotect and cannot be erased or programmed. also see note under accel- erate program operation above. standby operation when the system is not reading or writing to the device, it can place the device in the standby
12 r1.3/may 02 hy29lv320 mode. in this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the oe# input. the standby mode can invoked using two methods. the device enters the ce# controlled deep standby mode when the ce# and reset# pins are both held at v cc 0.3v. note that this is a more restricted voltage range than v ih . if both ce# and reset# are held at v ih , but not within v cc 0.3v, the device will be in the normal standby mode, but the standby current will be greater. note: if the device is deselected during erasure or programming, it continues to draw active current until the operation is completed. the device enters the reset# controlled deep standby mode when the reset# pin is held at v ss 0.3v. if reset# is held at v il but not within v ss 0.3v, the standby current will be greater. see reset# section for additional information on the reset operation. the device requires standard access time (t ce ) for read access when the device is in any of the standby modes before it is ready to read data. sleep mode the sleep mode automatically minimizes device power consumption. this mode is automatically entered when addresses remain stable for t acc + 30 ns (typical) and is independent of the state of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. the device does not enter sleep mode if an automatic program or automatic erase algo- rithm is in progress. output disable operation when the oe# input is at v ih , output data from the device is disabled and the data bus pins are placed in the high impedance state. reset operation the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for the minimum specified period, the device immediately termi- nates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. if an operation was interrupted by the as- sertion of reset#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. current is reduced for the duration of the reset# pulse as described in the standby operation sec- tion. if reset# is asserted during a program or erase operation (ry/by# pin is low), the ry/by# pin remains low (busy) until the internal reset opera- tion is complete, which requires a time of t ready (during automatic algorithms). the system can thus monitor ry/by# to determine when the reset operation completes, and can perform a read or write operation t rb after ry/by# goes high. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is high), the reset operation is completed within a time of t rp . in this case, the host can perform a read or write operation t rh after the reset# pin returns high. the reset# pin may be tied to the system reset signal. thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the flash memory. sector group protect operation the hardware sector group protection feature dis- ables both program and erase operations in any combination of sector groups. a sector group con- sists of a single sector or a group of adjacent sec- tors, as specified in tables 6 and 7. this function can be implemented either in-system or by using programming equipment. it requires a high volt- age (v id ) on the reset# pin and uses standard microprocessor bus cycle timing to implement sector protection. the flow chart in figure 3 illus- trates the algorithm. the hy29lv320 is shipped with all sectors un- protected. it is possible to determine whether a sector is protected or unprotected. see the elec- tronic id mode section for details. sector unprotect operation the hardware sector unprotection feature re-en- ables both program and erase operations in pre-
13 r1.3/may 02 hy29lv320 viously protected sector groups. this function can be implemented either in-system or by using pro- gramming equipment. note that to unprotect any sector, all unprotected sector groups must first be protected prior to the first sector unprotect write cycle. also, the unprotect procedure will cause all sectors to become unprotected, thus, sector groups that require protection must be protected again after the unprotect procedure is run. this procedure requires v id on the reset# pin and uses standard microprocessor bus cycle tim- ing to implement sector unprotection. the flow chart in figure 4 illustrates the algorithm. temporary sector unprotect operation this feature allows temporary unprotection of pre- viously protected sector groups to allow changing the data in-system. temporary sector unprotect mode is activated by setting the reset# pin to v id . while in this mode, formerly protected sec- p u o r g s r o t c e s ) 1 e l b a t ( s s e r d d a p u o r g ] 2 1 : 0 2 [ a e z i s k c o l b ) s d r o w k ( 0 g s0 s 000000xxx 2 3 1 g s3 s - 1 s 000001xxx 6 9 000010xxx 000011xxx 2 g s7 s - 4 s 0 0 0 1xxxxx 8 2 1 3 g s1 1 s - 8 s 0 0 10xxxxx 8 2 1 4 g s5 1 s - 2 1 s 0 0 1 1xxxxx 8 2 1 5 g s9 1 s - 6 1 s 0 10 0xxxxx 8 2 1 6 g s3 2 s - 0 2 s 0 10 1xxxxx 8 2 1 7 g s7 2 s - 4 2 s 0 1 10xxxxx 8 2 1 8 g s1 3 s - 8 2 s 0 1 1 1xxxxx 8 2 1 9 g s5 3 s - 2 3 s 10 0 0xxxxx 8 2 1 0 1 g s9 3 s - 6 3 s 10 0 1xxxxx 8 2 1 1 1 g s3 4 s - 0 4 s 10 10xxxxx 8 2 1 2 1 g s7 4 s - 4 4 s 10 1 1xxxxx 8 2 1 3 1 g s1 5 s - 8 4 s 1 10 0xxxxx 8 2 1 4 1 g s5 5 s - 2 5 s 1 10 1xxxxx 8 2 1 5 1 g s9 5 s - 6 5 s 1 1 10xxxxx 8 2 1 6 1 g s2 6 s - 0 6 s 111100xxx 6 9 111101xxx 111110xxx 7 1 g s3 6 s 1111110xx 6 1 8 1 g s4 6 s 111111100 4 9 1 g s5 6 s 111111101 4 0 2 g s6 6 s 11111111x 8 p u o r g s r o t c e s ) 2 e l b a t ( s s e r d d a p u o r g ] 2 1 : 0 2 [ a e z i s k c o l b ) s d r o w k ( 0 g s0 s 00000000x 8 1 g s1 s 0000000 10 4 2 g s2 s 000000011 4 3 g s3 s 0000001xx 6 1 4 g s6 s - 4 s 000001xxx 6 9 000010xxx 000011xxx 5 g s0 1 s - 7 s 0 0 0 1xxxxx 8 2 1 6 g s4 1 s - 1 1 s 0 0 10xxxxx 8 2 1 7 g s8 1 s - 5 1 s 0 0 1 1xxxxx 8 2 1 8 g s2 2 s - 9 1 s 0 10 0xxxxx 8 2 1 9 g s6 2 s - 3 2 s 0 10 1xxxxx 8 2 1 0 1 g s0 3 s - 7 2 s 0 1 10xxxxx 8 2 1 1 1 g s4 3 s - 1 3 s 0111xxxxx 8 2 1 2 1 g s8 3 s - 5 3 s 10 0 0xxxxx 8 2 1 3 1 g s2 4 s - 9 3 s 10 0 1xxxxx 8 2 1 4 1 g s6 4 s - 3 4 s 10 10xxxxx 8 2 1 5 1 g s0 5 s - 7 4 s 10 1 1xxxxx 8 2 1 6 1 g s4 5 s - 1 5 s 1 10 0xxxxx 8 2 1 7 1 g s8 5 s - 5 5 s 1 10 1xxxxx 8 2 1 8 1 g s2 6 s - 9 5 s 1110xxxxx 8 2 1 9 1 g s5 6 s - 3 6 s 111100xxx 6 9 111101xxx 111110xxx 0 2 g s6 6 s 111111xxx 2 3 table 6. sector groups - top boot version table 7. sector groups - bottom boot version tors can be programmed or erased by invoking the appropriate commands (see device com- mands section). once v id is removed from re- set#, all the previously protected sector groups are protected again. figure 5 illustrates the algo- rithm. note: if wp#/acc = v il , the boot sectors remain pro- tected. electronic id operation (high voltage method) the electronic id mode provides manufacturer and device identification, sector protection verifi- cation and sec 2 region protection status through identifier codes output on dq[15:0]. this mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. two methods are provided for accessing the elec- tronic id data. the first requires v id on address pin a[9], with additional requirements for obtain-
14 r1.3/may 02 hy29lv320 figure 3. sector group protect algorithm start reset# = v id wp#/acc = v ih wait 1 us first write cycle: write 0x60 to device sector group protect: write 0x60 to address wait 150 us verify sector group protect: write 0x40 to address read from address data = 0x01? protect another sector group? yes trycnt = 25? no increment trycnt no yes device failure yes no reset# = v ih write reset command sector group protect complete trycnt = 1 set address: a[20:12] = address of sector group to be protected a[6] = 0, a[1] = 1, a[0] = 0 figure 4. sector unprotect algorithm start note: all sector groups must be protected prior to sector unprotection trycnt = 1 snum = 0 reset# = v id wp#/acc = v ih wait 1 us first write cycle: write 0x60 to device sector unprotect: write 0x60 to address set address: a[20:12] = address of sector group snum a[6] = 1, a[1] = 1, a[0] = 0 verify unprotect: write 0x40 to address read from address data = 0x00? snum = 20? yes trycnt = 1000? no increment trycnt no yes device failure yes no reset# = v ih write reset command sector unprotect complete snum = snum + 1 wait 15 ms set address: a[6] = 1, a[1] = 1, a[0] = 0
15 r1.3/may 02 hy29lv320 ing specific data items listed in table 5. the elec- tronic id data can also be obtained by the host through specific commands issued via the com- mand register, as described later in the ? device commands ? section of this data sheet. while in the high-voltage electronic id mode, the system may read at specific addresses to obtain certain device identification and status informa- tion: a read cycle at address 0xxxx00 retrieves the manufacturer code. a read cycle at address 0xxxx01 returns the device code. a read cycle containing a sector address (sa) in a[20:12] and the address 0x04 in a[7:0] re- turns 0x01 if that sector is protected, or 0x00 if it is unprotected. a read cycle at address 0xxxx03 returns 0x80 if the sec 2 region is protected and locked at the factory and 0x00 if it is not. figure 5. temporary sector unprotect algorithm start reset# = v id (all protected sectors become unprotected) perform program or erase operations reset# = v ih (all previously protected sectors return to protected state) temporary sector unprotect complete device commands device operations are initiated by writing desig- nated address and data command sequences into the device. commands are routed to the com- mand register for execution. this register is auto- matically selected as the destination for all write operations and does not need to be explicitly ad- dressed. addresses are latched on the falling edge of we# or ce#, whichever happens later. data is latched on the rising edge of we# or ce#, whichever happens first. a command sequence is composed of one, two or three of the following sub-segments: an unlock cycle , a command cycle and a data cycle . table 8 summarizes the composition of the valid com- mand sequences implemented in the hy29lv320, and these sequences are fully described in table 9 and in the sections that follow. writing incorrect address and data values or writ- ing them in the improper sequence resets the de- vice to the read mode. reading data the device automatically enters the read array mode after device power-up, after the reset# input is asserted and upon the completion of cer- tain commands. commands are not required to d n a m m o c e c n e u q e s s e l c y c s u b f o r e b m u n k c o l n u d n a m m o c a t a d d a e r001 e t o n t e s e r010 c e s r e t n e 2 n o i g e r210 c e s t i x e 2 n o i g e r211 m a r g o r p211 s s a p y b k c o l n u210 s s a p y b k c o l n u t e s e r 01 1 s s a p y b k c o l n u m a r g o r p 01 1 e s a r e p i h c411 e s a r e r o t c e s41) 2 e t o n ( 1 d n e p s u s e s a r e010 e m u s e r e s a r e010 d i c i n o r t c e l e213 e t o n y r e u q i f c014 e t o n notes: 1. any number of flash array read cycles are permitted. 2. additional data cycles may follow. see text. 3. any number of electronic id read cycles are permitted. 4. any number of cfi data read cycles are permitted. table 8. composition of command sequences
16 r1.3/may 02 hy29lv320 retrieve data in this mode. see read operation section for additional information. after the device accepts an erase suspend com- mand, the hy29lv320 enters the erase-suspend- read mode, after which the system can read data from any non-erase-suspended sector. after com- pleting a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. reset command writing the reset command resets the sectors to the read or erase-suspend mode. address bits are don ? t cares for this command. as described above, a reset command is not nor- mally required to begin reading array data. how- ever, a reset command must be issued in order to read array data in the following cases: if the device is in the electronic id mode, a reset command must be written to return to the read array mode. if the device was in the erase suspend mode when the device entered the electronic id mode, writing the reset com- mand returns the device to the erase suspend mode. note: when in the electronic id bus operation mode, the device returns to the read array mode when v id is removed from the a[9] pin. the reset command is not required in this case. if the device is in the cfi query mode, a reset command must be written to return to the ar- ray read mode. if dq[5] (exceeded time limit) goes high dur- ing a program or erase operation, a reset com- mand must be invoked to return the sectors to the read mode (or to the erase suspend mode if the device was in erase suspend when the program command was issued). the reset command may also be used to abort certain command sequences: in a sector erase or chip erase command se- quence, the reset command may be written at any time before erasing actually begins, in- cluding, for the sector erase command, be- tween the cycles that specify the sectors to be erased (see sector erase command descrip- tion). this aborts the command and resets the device to the read mode. once erasure be- gins, however, the device ignores the reset command until the operation is complete. in a program command sequence, the reset command may be written between the se- quence cycles before programming actually be- gins. this aborts the command and resets the device to the read mode, or to the erase sus- pend mode if the program command sequence is written while the device is in the erase sus- pend mode. once programming begins, how- ever, the device ignores the reset command until the operation is complete. the reset command may be written between the cycles in an electronic id command se- quence to abort that command. as described above, once in the electronic id mode, the reset command must be written to return to the array read mode. note : the reset command does not return the device from sec 2 region access to normal array access. see descriptions of enter/exit sec 2 region commands for additional information. enter/exit sec 2 region command sequences the system can access the sec 2 region of the device by issuing the enter sec 2 region command sequence. the device continues to access the sec 2 region until the system issues the exit sec 2 region command sequence, which returns the device to normal operation. note that a hardware reset will reset the device to the read array mode. program command sequence the system programs the device a word at a time by issuing the appropriate four-cycle program command sequence as shown in table 9. the sequence begins by writing two unlock cycles, fol- lowed by the program setup command and, lastly, the program address and data. this initiates the automatic program algorithm that automatically provides internally generated program pulses and verifies the programmed cell margin. the host is not required to provide further controls or timings during this operation. when the automatic pro- gram algorithm is complete, the device returns to the reading array data mode. several methods are provided to allow the host to determine the
17 r1.3/may 02 hy29lv320 table 9. hy29lv320 command sequences s e l c y c s u b 4 , 3 , 2 , 1 e c n e u q e s d n a m m o c e t i r w s e l c y c t s r i f d n o c e s d r i h t h t r u o f h t f i f h t x i s d d a a t a d d d a a t a d d d a a t a d d d a a t a d d d a a t a d d d a a t a d d a e r0a rd r t e s e r 7 1x x x0 f c e s r e t n e 2 n o i g e r35 5 5a aa a 25 55 5 58 8 c e s t i x e 2 n o i g e r45 5 5a aa a 25 55 5 50 9 x x x 0 0 m a r g o r p l a m r o n45 5 5a aa a 25 55 5 50 aa pd p s s a p y b k c o l n u35 5 5a aa a 25 55 5 5 0 2 t e s e r s s a p y b k c o l n u 6 2x x x0 9x x x0 0 m a r g o r p s s a p y b k c o l n u 5 2x x x0 aa pd p e s a r e p i h c65 5 5a aa a 25 55 5 50 85 5 5a aa a 25 55 5 50 1 e s a r e r o t c e s 9 65 5 5a aa a 25 55 5 50 85 5 5a aa a 25 5a s0 3 d n e p s u s e s a r e 7 1x x x0 b e m u s e r e s a r e 8 1x x x0 3 e d o c r e r u t c a f u n a m35 5 5a aa a 25 55 5 50 90 0 x x xd a 0 0 e d o c e c i v e d35 5 5a aa a 25 55 5 50 91 0 x x xe 7 2 2 = t o o b p o t , d 7 2 2 = t o o b m o t t o b y f i r e v t c e t o r p r o t c e s35 5 5a aa a 25 55 5 50 92 0 x ) a s ( r o t c e s d e t c e t o r p n u = 0 0 x x r o t c e s d e t c e t o r p = 1 0 x x c e s 2 t i b r o t a c i d n i n o i g e r 35 5 5a aa a 2 5 5 5 5 5 0 9 3 0 x x x y r o t c a f t a d e k c o l d n a d e t c e t o r p t o n = 0 0 x x y r o t c a f t a d e k c o l d n a d e t c e t o r p = 0 8 x x y r e u q ) i f c ( e c a f r e t n i h s a l f n o m m o c 0 1 1 5 5 x x x 8 9 electronic id 11 legend: x = don ? t care ra/rd = memory address/data for the read operation pa/pd = memory address/data for the program operation sa = a[20:12], sector address of the sector to be erased or verified (see tables 1 and 2). notes: 1. all values are in hexadecimal. 2. all bus cycles are write operations except all cycles of the read command and the fourth cycle of electronic id command. 3. data bits dq[15:8] are don ? t cares except for ? pd ? in program cycles. 4. address is a[10:0]. other (upper) address bits are don ? t cares except when ? sa ? or ? pa ? is required. 5. the unlock bypass command is required prior to the unlock bypass program command. 6. the unlock bypass reset command is valid only while the device is in the unlock bypass mode. 7. the erase suspend command is valid only during a sector erase operation. the system may read and program in non-erasing sect ors, or enter the electronic id mode, while in the erase suspend mode. 8. the erase resume command is valid only during the erase suspend mode. 9. multiple sectors may be specified for erasure. see command description. 10.see cfi section of specification for additional information. 11. see electronic id section of specification for additional information.
18 r1.3/may 02 hy29lv320 status of the programming operation, as described in the write operation status section. commands written to the device during execution of the automatic program algorithm are ignored. note that a hardware reset immediately terminates the programming operation (see reset operation timings). to ensure data integrity, the user should reinitiate the aborted program command se- quence after the reset operation is complete. programming is allowed in any sequence. only erase operations can convert a stored ? 0 ? to a ? 1 ? . thus, a bit cannot be programmed from a ? 0 ? back to a ? 1 ? . attempting to do so will cause the hy29lv320 to halt the operation and set dq[5] to ? 1 ? , or cause the data# polling algorithm to indi- cate the operation was successful. however, a succeeding read will show that the data is still ? 0 ? . figure 6 illustrates the programming operation. unlock bypass command sequence unlock bypass provides a faster method than the normal program command for the host system to program the array. as shown in table 9, the un- lock bypass command sequence consists of two unlock write cycles followed by a third write cycle containing the unlock bypass command, 0x20. the device then enters unlock bypass mode. in this mode, a two-cycle unlock bypass program command sequence is used instead of the stan- dard four-cycle sequence to invoke a program- ming operation. the first cycle in this sequence contains the unlock bypass program command, 0xa0, and the second cycle specifies the program address and data, thus eliminating the initial two unlock cycles required in the standard program command sequence. additional data is pro- grammed in the same manner. the unlock by- pass mode does not affect normal read operations. during the unlock bypass mode, only the unlock bypass program and the unlock bypass reset commands are valid. to exit the unlock bypass mode, the host must issue the two-cycle unlock bypass reset command sequence shown in table 9. figure 6 illustrates the procedures for the normal and unlock bypass program operations. the device automatically enters the unlock bypass mode when it is placed in accelerate mode via the acc pin. start enable fast programming? issue unlock bypass command yes no unlock bypass mode? issue unlock bypass program command issue normal program command check programming status (see write operation status section) yes no last word/byte done? yes no setup next address/data for program operation yes no unlock bypass mode? issue unlock bypass reset command programming complete go to error recovery procedure dq[5] error exit programming verified figure 6. normal and unlock bypass programming procedures
19 r1.3/may 02 hy29lv320 chip erase command sequence the chip erase command sequence consists of two unlock cycles, followed by a set-up command, two additional unlock cycles and then the chip erase command. this sequence invokes the automatic chip erase algorithm which automati- cally preprograms (if necessary) and verifies the entire memory for an all zero data pattern before electrical erase. the host system is not required to provide any controls or timings during these operations. if all sectors in the device are protected, the de- vice returns to reading array data after approxi- mately 100 s. if at least one sector is unpro- tected, the erase operation erases the unprotected sectors, and ignores the command for the sectors that are protected. reads from the device during operation of the automatic chip erase algorithm return status data. see write operation status section of this specification. commands written to the device during execution of the automatic chip erase algorithm are ignored. note that a hardware reset immediately terminates the chip erase operation (see hardware reset tim- ings). to ensure data integrity, the user should reinitiate the aborted chip erase command se- quence after the reset operation is complete. when the automatic chip erase algorithm is com- plete, the device returns to the reading array data mode. several methods are provided to allow the host to determine the status of the erase opera- tion, as described in the write operation status section. figure 7 illustrates the chip erase procedure. sector erase command sequence the sector erase command sequence consists of two unlock cycles, followed by a set-up com- mand, two additional unlock cycles and then the sector erase command, which specifies which sector is to be erased. this sequence invokes the automatic sector erase algorithm which auto- matically preprograms (if necessary) and verifies the specified sector for an all zero data pattern before electrical erase. the host system is not required to provide any controls or timings during these operations. after the sector erase command cycle (sixth cycle) of the command sequence is issued, a sector erase time-out of 50 s (min) begins, measured from the rising edge of the final we# pulse in the command sequence. during this time, an addi- tional sector address and sector erase command may be written into an internal sector erase buffer. this buffer may be loaded in any sequence, and the number of sectors designated for erasure may be from one sector to all sectors. the only re- striction is that the time between these additional cycles must be less than 50 s, otherwise era- sure may begin before the last address and com- mand are accepted. to ensure that all commands are accepted, it is recommended that host pro- cessor interrupts be disabled during the time that the additional sector erase commands are being issued and then be re-enabled afterwards. the system can monitor dq[3] to determine if the 50 s sector erase time-out has expired, as de- scribed in the write operation status section. if the time between additional sector erase com- mands can be assured to be less than the time- out, the system need not monitor the timeout. note: any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must then rewrite the command sequence, including any additional sector addresses and commands. once the sector erase op- eration itself has begun, only the erase suspend com- mand is valid. all other commands are ignored. as for the chip erase command, note that a hard- ware reset immediately terminates the erase op- eration (see hardware reset timings). to ensure data integrity, the aborted sector erase command sequence should be reissued once the reset op- eration is complete. start issue chip erase command sequence check erase status (see write operation status section) chip erase complete go to error recovery dq[5] error exit normal exit figure 7. chip erase procedure
20 r1.3/may 02 hy29lv320 if all sectors designated for erasing are protected, the device returns to reading array data after ap- proximately 100 s. if at least one designated sector is unprotected, the erase operation erases the unprotected sectors, and ignores the command for the sectors that are protected. read array operations cannot take place until the automatic erase algorithm terminates, or until the erase op- eration is suspended. read operations while the algorithm is in progress provide status data. when the automatic erase algorithm is complete, the device returns the erased sector(s) to the read (array data) mode. several methods are provided to allow the host to determine the status of the erase operation, as described in the write operation status section. figure 8 illustrates the sector erase procedure. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation to program data into, or to read data from, any sector not designated for erasure. the command causes the erase operation to be suspended in all sec- tors designated for erasure. this command is valid only during the sector erase operation, including during the 50 s time-out period at the end of the command sequence, and is ignored if it is issued during chip erase or programming operations. the hy29lv320 requires a maximum of 20 s to suspend the erase operation if the erase suspend command is issued during active sector erasure. however, if the command is written during the sector erase time-out, the time-out is terminated and the erase operation is suspended immediately. once the erase operation has been suspended, the system can read array data from or program data into any sector that is not designated for era- sure (protected sectors cannot be programmed). normal read and write timings and command defi- nitions apply. reading at any address within erase- suspended sectors produces status data on dq[7:0]. the host can use dq[7], or dq[6] and dq[2] together, to determine if a sector is actively erasing or is erase-suspended. see ? write op- eration status ? for information on these status bits. after an erase-suspended program operation is complete, the device returns to the erase-sus- pended read state and the host can initiate an- other programming operation (or read operation) within non-suspended sectors. the host can de- termine the status of a program operation during the erase-suspended state just as in the standard programming operation. figure 8. sector erase procedure start yes erase an additional sector? check erase status (see write operation status section) setup first (or next) sector address for erase operation erase complete write first five cycles of sector erase command sequence write last cycle (sa/0x30) of sector erase command sequence sector erase time-out (dq[3]) expired? no yes no go to error recovery dq[5] error exit normal exit sectors that require erasure but which were not specified in this erase cycle must be erased later using a new command sequence
21 r1.3/may 02 hy29lv320 the host may also write the electronic id com- mand sequence when the chip is in the erase suspend mode. the device allows reading elec- tronic id codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the elec- tronic id mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see electronic id mode section for more information. the system must write the erase resume com- mand to exit the erase suspend mode and con- tinue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the de- vice has resumed erasing. note : if an erase operation is started while in the sec 2 region and then suspended to do other operations, the host must return the device to the sec 2 region before issuing the erase resume command. failure to do this may result in the wrong sector being erased. electronic id command the electronic id mode provides manufacturer and device identification and sector protection veri- fication through identifier codes output on dq[15:0]. this mode is intended primarily for pro- gramming equipment to automatically match a device to be programmed with its corresponding programming algorithm. two methods are provided for accessing the elec- tronic id data. the first requires v id on address pin a[9], as described previously in the device operations section. the electronic id data can also be obtained by the host through specific commands issued via the com- mand register, as shown in table 9. this method does not require v id . the electronic id command sequence may be issued while the device is in the read mode or in the erase suspend read mode. the command may not be written while the device is actively programming or erasing. the electronic id command sequence is initiated by writing two unlock cycles, followed by a third write cycle that contains the electronic id com- mand. the device then enters the electronic id mode, and the system may read at any address any number of times without initiating another com- mand sequence. a read cycle at address 0xxxx00 retrieves the manufacturer code. a read cycle at address 0xxxx01 in returns the device code. a read cycle containing a sector address (sa) in a[20:12] and the address 0x02 in a[7:0] re- turns 0x01 if that sector is protected, or 0x00 if it is unprotected. a read cycle at address 0xxxx03 returns 0x80 if the sec 2 region is protected and locked at the factory and returns 0x00 if it is not. the system must write the reset command to exit the electronic id mode and return the bank to the normal read mode, or to the erase-suspended read mode if the device was in that mode when the electronic id command was invoked. in the latter case, an erase resume command to that bank will continue the suspended erase operation. query command and common flash inter- face (cfi) mode the hy29lv320 is capable of operating in the common flash interface (cfi) mode. this mode allows the host system to determine the manufac- turer of the device, its operating parameters, its configuration and any special command codes that the device may accept. with this knowledge, the system can optimize its use of the chip by using appropriate timeout values, optimal voltages and commands necessary to use the chip to its full advantage. two commands are employed in association with cfi mode. the first places the device in cfi mode (query command) and the second takes it out of cfi mode (reset command). these are described in table 10. the single cycle query command is valid only when the device is in the read mode, including during erase suspend and standby states and while in electronic id command mode, but is ig- nored otherwise. the command is not valid while the hy29lv320 is in the electronic id bus opera- tion mode. read cycles at appropriate addresses while in the query mode provide cfi data as de- scribed later in this section. write cycles are ig- nored, except for the reset command. the reset command returns the device from the cfi mode to the array read mode (even if it was
22 r1.3/may 02 hy29lv320 in the electronic id mode when the query com- mand was issued), or to the erase suspend mode if the device was in that mode prior to entering cfi mode. the reset command is valid only when the device is in the cfi mode and as otherwise described for the normal reset command. n o i t p i r c s e d s s e r d d a a t a d " y r q " g n i r t s i i c s a e u q i n u - y r e u q 0 1 1 1 2 1 1 5 0 0 2 5 0 0 9 5 0 0 e d o c d i e c a f r e t n i l o r t n o c d n a t e s d n a m m o c r o d n e v y r a m i r p 3 1 4 1 2 0 0 0 0 0 0 0 e l b a t y r e u q d e d n e t x e m h t i r o g l a y r a m i r p r o f s s e r d d a 5 1 6 1 0 4 0 0 0 0 0 0 ) e n o n ( e d o c d i e c a f r e t n i l o r t n o c d n a t e s d n a m m o c r o d n e v e t a n r e t l a 7 1 8 1 0 0 0 0 0 0 0 0 ) e n o n ( e l b a t y r e u q d e d n e t x e m h t i r o g l a y r a d n o c e s r o f s s e r d d a 9 1 a 1 0 0 0 0 0 0 0 0 table 10. cfi mode: identification data values tables 10 - 13 specify the data provided by the hy29lv320 during cfi mode. data at unspeci- fied addresses reads out as 0x00. note that a value of 0x00 for a data item normally indicates that the function is not supported. all values in these tables are in hexadecimal notation.
23 r1.3/may 02 hy29lv320 n o i t p i r c s e d s s e r d d a a t a d v c c ) v 7 . 2 ( m u m i n i m , y l p p u s b 17 2 0 0 v c c ) v 6 . 3 ( m u m i x a m , y l p p u s c 16 3 0 0 v p p ) e n o n ( m u m i n i m , y l p p u s d 10 0 0 0 v p p ) e n o n ( m u m i x a m , y l p p u s e 10 0 0 0 2 ( e t i r w e t y b / d r o w e l g n i s r o f t u o e m i t l a c i p y t n ) s f 14 0 0 0 2 ( e t i r w r e f f u b e z i s m u m i x a m r o f t u o e m i t l a c i p y t n ) s 0 20 0 0 0 2 ( e s a r e k c o l b l a u d i v i d n i r o f t u o e m i t l a c i p y t n ) s m1 29 0 0 0 2 ( e s a r e p i h c l l u f r o f t u o e m i t l a c i p y t n ) s m2 2f 0 0 0 2 ( e t i r w e t y b / d r o w e l g n i s r o f t u o e m i t m u m i x a m n ) p y t x3 25 0 0 0 2 ( e t i r w r e f f u b e z i s m u m i x a m r o f t u o e m i t m u m i x a m n ) p y t x4 20 0 0 0 2 ( e s a r e k c o l b l a u d i v i d n i r o f t u o e m i t m u m i x a m n ) p y t x5 24 0 0 0 ) d e t r o p p u s t o n ( e s a r e p i h c l l u f r o f t u o e m i t m u m i x a m 6 20 0 0 0 table 11. cfi mode: system interface data values n o i t p i r c s e d s s e r d d a a t a d 2 ( e z i s e c i v e d n ) s e t y b7 26 1 0 0 e d o c e c a f r e t n i e c i v e d h s a l f ) 6 1 x s u o n o r h c n y s a = 1 0 ( 8 2 9 2 1 0 0 0 0 0 0 0 ) d e t r o p p u s t o n ( e t i r w e t y b - i t l u m n i s e t y b f o r e b m u n m u m i x a m a 2 b 2 0 0 0 0 0 0 0 0 s n o i g e r k c o l b e s a r e f o r e b m u n c 24 0 0 0 n o i t a m r o f n i 1 n o i g e r k c o l b e s a r e 1 - n o i g e r n i s k c o l b f o # = ] d 2 , e 2 [ s e t y b - 6 5 2 f o s e l p i t l u m n i e z i s = ] f 2 , 0 3 [ d 2 e 2 f 2 0 3 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 n o i t a m r o f n i 2 n o i g e r k c o l b e s a r e 1 3 2 3 3 3 4 3 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 n o i t a m r o f n i 3 n o i g e r k c o l b e s a r e 5 3 6 3 7 3 8 3 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 n o i t a m r o f n i 4 n o i g e r k c o l b e s a r e 9 3 a 3 b 3 c 3 e 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 table 12. cfi mode: device geometry data values
24 r1.3/may 02 hy29lv320 n o i t p i r c s e d s s e r d d a a t a d " i r p " g n i r t s i i c s a e u q i n u - y r e u q 0 4 1 4 2 4 0 5 0 0 2 5 0 0 9 4 0 0 i i c s a , r e b m u n n o i s r e v r o j a m 3 41 3 0 0 i i c s a , r e b m u n n o i s r e v r o n i m 4 40 3 0 0 k c o l n u e v i t i s n e s s s e r d d a) d e r i u q e r t o n = 1 , d e r i u q e r = 0 (5 40 0 0 0 ) e t i r w d n a d a e r o t = 2 ( d n e p s u s e s a r e 6 42 0 0 0 ) p u o r g / s r o t c e s f o # = n ( t c e t o r p r o t c e s 7 41 0 0 0 t c e t o r p n u r o t c e s y r a r o p m e t) d e t r o p p u s = 1 (8 41 0 0 0 e m e h c s t c e t o r p n u / t c e t o r p r o t c e s) d o h t e m a 0 0 8 v l 9 2 m a = 4 (9 44 0 0 0 n o i t a r e p o w / r s u o e n a t l u m i s ) d e t r o p p u s t o n = 0 : 2 k n a b n i s r o t c e s f o r e b m u n = x x ( a 40 0 0 0 ) d e t r o p p u s t o n = 0 ( e p y t e d o m t s r u b b 40 0 0 0 e p y t e d o m e g a p) d e t r o p p u s t o n = 0 (c 40 0 0 0 ) v 5 . 1 1 ( m u m i n i m y l p p u s c c a d 45 b 0 0 ) v 5 . 2 1 ( m u m i x a m y l p p u s c c a e 45 c 0 0 ) t o o b p o t = b t , t o o b m o t t o b = b b ( n o i s r e v t o o b m o t t o b / p o t f 4 ) b b ( 2 0 0 0 ) b t ( 3 0 0 0 table 13. cfi mode: vendor-specific extended query data values write operation status the hy29lv320 provides a number of facilities to determine the status of a program or erase op- eration. these are the ry/by# (ready/busy#) pin and certain bits of a status word which can be read from the device during the programming and erase operations. table 11 summarizes the sta- tus indications and further detail is provided in the subsections which follow. ry/by# - ready/busy# ry/by# is an open-drain output pin that indicates whether a programming or erase automatic algo- rithm is in progress or has completed. a pull-up resistor to v cc is required for proper operation. ry/ by# is valid after the rising edge of the final we# pulse in the corresponding command sequence. if the output is low (busy), the device is actively erasing or programming, including programming while in the erase suspend mode. if the output is high (ready), the device has completed the opera- tion and is ready to read array data in the normal or erase suspend modes, or it is in the standby mode. dq[7] - data# polling the data# ( ? data bar ? ) polling bit, dq[7], indicates to the host system whether an automatic algo- rithm is in progress or completed, or whether the device is in erase suspend mode. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. the system must do a read at the program ad- dress to obtain valid programming status informa- tion on this bit. while a programming operation is in progress, the device outputs the complement of the value programmed to dq[7]. when the pro- gramming operation is complete, the device out- puts the value programmed to dq[7]. if a pro- gram operation is attempted within a protected sector, data# polling on dq[7] is active for ap- proximately 1 s, then the device returns to read- ing array data. the host must read at an address within any non- protected sector specified for erasure to obtain valid erase status information on dq[7]. during an erase operation, data# polling produces a ? 0 ? on dq[7]. when the erase operation is complete, or if the device enters the erase suspend mode, data# polling produces a ? 1 ? on dq[7]. if all sec- tors selected for erasing are protected, data# polling on dq[7] is active for approximately 100 s, then the device returns to reading array data. if at least one selected sector is not protected, the erase operation erases the unprotected sectors,
25 r1.3/may 02 hy29lv320 and ignores the command for the specified sec- tors that are protected. when the system detects that dq[7] has changed from the complement to true data (or ? 0 ? to ? 1 ? for erase), it should do an additional read cycle to read valid data from dq[7:0]. this is because dq[7] may change asynchronously with respect to the other data bits while output enable (oe#) is as- serted low. figure 9 illustrates the data# polling test algorithm. dq[6] - toggle bit i toggle bit i on dq[6] indicates whether an auto- matic program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the program or erase command sequence, including during the sector erase time-out. the system may use either oe# or ce# to control the read cycles. successive read cycles at any address during an automatic program algorithm operation (including programming while in erase suspend mode) cause dq[6] to toggle. dq[6] stops toggling when the op- eration is complete. if a program address falls within table 14. write and erase operation status summary 1 notes: 1. a valid address is required when reading status information (except ry/by#). for a programming operation, the ad- dress used for the read cycle should be the program address. for an erase operation, the address used for the read cycle should be any address within a non-protected sector marked for erasure (any address within a non-protected sector for the chip erase operation). 2. dq[5] status switches to a ? 1 ? when a program or erase operation exceeds the maximum timing limit. 3. a ? 1 ? during sector erase indicates that the 50 s time-out has expired and active erasure is in progress. dq[3] is not applicable to the chip erase operation. 4. equivalent to ? no toggle ? because data is obtained in this state. 5. data (dq[7:0]) = 0xff immediately after erasure. 6. programming can be done only in a non-suspended sector (a sector not specified for erasure). e d o m n o i t a r e p o ] 7 [ q d ] 6 [ q d ] 5 [ q d ] 3 [ q d ] 2 [ q d # y b / y r l a m r o n s s e r g o r p n i g n i m m a r g o r p# ] 7 [ q de l g g o t1 / 0 2 a / na / n0 d e t e l p m o c g n i m m a r g o r pa t a da t a d 4 a t a da t a da t a d1 s s e r g o r p n i e s a r e0e l g g o t1 / 0 2 1 3 e l g g o t0 d e t e l p m o c e s a r e 5 a t a da t a d 4 a t a da t a da t a d 4 1 e s a r e d n e p s u s d e d n e p s u s e s a r e n i h t i w d a e r r o t c e s 1e l g g o t o n0a / ne l g g o t1 e s a r e - n o n n i h t i w d a e r r o t c e s d e d n e p s u s a t a da t a da t a da t a da t a d1 s s e r g o r p n i g n i m m a r g o r p 6 # ] 7 [ q de l g g o t1 / 0 2 a / na / n0 d e t e l p m o c g n i m m a r g o r p 6 a t a da t a d 4 a t a da t a da t a d1 a protected sector, dq[6] toggles for approximately 1 s after the program command sequence is writ- ten, then returns to reading array data. while the automatic erase algorithm is operating, successive read cycles at any address cause dq[6] to toggle. dq[6] stops toggling when the erase operation is complete or when the device is placed in the erase suspend mode. the host may use dq[2] to determine which sectors are erasing or erase-suspended (see below). after an erase command sequence is written, if all sectors se- lected for erasing are protected, dq[6] toggles for approximately 100 s, then returns to reading ar- ray data. if at least one selected sector is not protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. dq[2] - toggle bit ii toggle bit ii, dq[2], when used with dq[6], indi- cates whether a particular sector is actively eras- ing or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. the device toggles dq[2] with each oe# or ce# read cycle.
26 r1.3/may 02 hy29lv320 start read dq[7:0] at valid address (note 1) dq[7] = data? no yes program/erase complete dq[5] = 1? no yes test for dq[7] = 1? for erase operation read dq[7:0] at valid address (note 1) dq[7] = data? (note 2) no yes test for dq[7] = 1? for erase operation program/erase exceeded time error notes: 1. during programming , the program address. during sector erase , an address within any non-protected sector specified for erasure. during chip erase , an address within any non-protected sector. 2. recheck dq[7] since it may change asynchronously to dq[5]. figure 9. data# polling test algorithm dq[2] toggles when the host reads at addresses within sectors that have been specified for era- sure, but cannot distinguish whether the sector is actively erasing or is erase-suspended. dq[6], by comparison, indicates whether the device is ac- tively erasing or is in erase suspend, but cannot distinguish which sectors are specified for erasure. thus, both status bits are required for sector and mode information. figure 10 illustrates the operation of toggle bits i and ii. dq[5] - exceeded timing limits dq[5] is set to a ? 1 ? when the program or erase time has exceeded a specified internal pulse count limit. this is a failure condition that indicates that the program or erase cycle was not successfully completed. dq[5] status is valid only while dq[7] or dq[6] indicate that the automatic algorithm is in progress. the dq[5] failure condition will also be signaled if the host tries to program a ? 1 ? to a location that is previously programmed to ? 0 ? , since only an erase operation can change a ? 0 ? to a ? 1 ? . for both of these conditions, the host must issue a reset command to return the device to the read mode. note: while dq[5] indicates an error condition, no com- mands (except reads) will be accepted by the device. if the device receives a command while dq[5] is high, the first write cycle of that command will reset the error con- dition and the remaining write cycles of that command sequence will be ignored dq[3] - sector erase timer after writing a sector erase command sequence, the host may read dq[3] to determine whether or not an erase operation has begun. when the sector erase time-out expires and the sector erase operation commences, dq[3] switches from a ? 0 ? to a ? 1 ? . refer to the ? sector erase command ? section for additional information. note that the sector erase timer does not apply to the chip erase command. after the initial sector erase command sequence is issued, the system should read the status on dq[7] (data# polling) or dq[6] (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq[3]. if dq[3] is a ? 1 ? , the internally controlled erase cycle has begun and all further sector erase data cycles or commands (other than erase suspend) are ignored until the erase operation is complete. if dq[3] is a ? 0 ? , the device will accept a sector erase data cycle to mark an additional sector for erasure. to ensure that the data cycles have been accepted, the system software should check the status of dq[3] prior to and following each subsequent sector erase data cycle. if dq[3] is high on the second status check, the last data cycle might not have been accepted.
27 r1.3/may 02 hy29lv320 read dq[7:0] at valid address (note 1) dq[6] toggled? no (note 3) yes program/erase complete dq[5] = 1? no yes read dq[7:0] at valid address (note 1) dq[6] toggled? (note 2) no yes program/erase exceeded time error notes : 1. during programming, the program address. during sector erase, an address within any sector scheduled for erasure. 2. recheck dq[6] since toggling may stop at the same time as dq[5] changes from 0 to 1. 3. use this path if testing for program/erase status. 4. use this path to test whether sector is in erase suspend mode. read dq[7:0] at valid address (note 1) start read dq[7:0] dq[2] toggled? no sector being read is in erase suspend read dq[7:0] yes no (note 4) sector being read is not in erase suspend figure 10. toggle bit i and ii test algorithm hardware data protection the hy29lv320 provides several methods of pro- tection to prevent accidental erasure or program- ming which might otherwise be caused by spuri- ous system level signals during v cc power-up and power-down transitions, or from system noise. these methods are described in the sections that follow. command sequences commands that may alter array data require a sequence of cycles as described in table 9. this provides data protection against inadvertent writes. low v cc write inhibit to protect data during v cc power-up and power- down, the device does not accept write cycles when v cc is less than v lko (typically 2.4 volts). the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by asserting any one of the following conditions: oe# = v il , ce# = v ih , or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is auto- matically reset to the read mode on power-up. sector protection additional data protection is provided by the hy29lv320 ? s sector protect feature, described previously, which can be used to protect sensitive areas of the flash array from accidental or unau- thorized attempts to alter the data.
28 r1.3/may 02 hy29lv320 absolute maximum ratings 4 l o b m y s r e t e m a r a p e u l a v t i n u t g t s e r u t a r e p m e t e g a r o t s0 5 1 + o t 5 6 -c o t s a i b d e i l p p a r e w o p h t i w e r u t a r e p m e t t n e i b m a5 2 1 + o t 5 6 -c o v 2 n i v o t t c e p s e r h t i w n i p n o e g a t l o v s s : v c c 1 # t e s e r , c c a / # p w , # e o , ] 9 [ a 2 s n i p r e h t o l l a 1 0 . 4 + o t 5 . 0 - 5 . 2 1 + o t 5 . 0 - v ( o t 5 . 0 - c c ) 5 . 0 + v v v i s o t n e r r u c t i u c r i c t r o h s t u p t u o 3 0 0 2a m notes: 1. minimum dc voltage on input or i/o pins is ? 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0v for periods of up to 20 ns. see figure 11. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 12. 2. minimum dc input voltage on pins a[9], wp#/acc, oe#, and reset# is -0.5 v. during voltage transitions, a[9], wp#/ acc, oe#, and reset# may undershoot v ss to ? 2.0 v for periods of up to 20 ns. see figure 11. maximum dc input voltage on pins a[9], wp#/acc, oe# and reset# is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output at a time may be shorted to v ss . duration of the short circuit should be less than one second. 4. stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions 1 l o b m y s r e t e m a r a p e u l a v t i n u t a : e r u t a r e p m e t g n i t a r e p o t n e i b m a s e c i v e d e r u t a r e p m e t l a i c r e m m o c s e c i v e d e r u t a r e p m e t l a i r t s u d n i 0 7 + o t 0 5 8 + o t 0 4 - c o c o v c c e g a t l o v y l p p u s g n i t a r e p o2 e t o nv notes: 1. recommended operating conditions define those limits between which the functionality of the device is guaranteed. 2. see valid combinations table, page 43. 2.0 v v cc + 0.5 v v cc + 2.0 v 20 ns 20 ns 20 ns figure 11. maximum undershoot waveform figure 12. maximum overshoot waveform 0.8 v - 0.5 v - 2.0 v 20 ns 20 ns 20 ns
29 r1.3/may 02 hy29lv320 dc characteristics r e t e m a r a p n o i t p i r c s e d p u t e s t s e t 2 n i m p y t x a m t i n u i i l t n e r r u c d a o l t u p n iv n i v = s s v o t c c 0 . 1 a i t i l t n e r r u c d a o l t u p n i , ] 9 [ av 5 . 2 1 = ] 9 [ a5 3a i o l t n e r r u c e g a k a e l t u p t u ov t u o v = s s v o t c c 0 . 1 a i 1 c c v c c t n e r r u c d a e r e v i t c a 1 v = # e c l i , v = # e o h i , z h m 596 1a m z h m 124a m i 2 c c v c c t n e r r u c e t i r w e v i t c a 4 , 3 v = # e c l i ,v = # e o h i 0 20 3a m i 3 c c v c c p e e d d e l l o r t n o c # e c t n e r r u c y b d n a t s v = # e c c c , v 3 . 0 v = # t e s e r c c , v 3 . 0 v = c c a / # p w c c v 3 . 0 v r o s s v 3 . 0 5 . 05a i 4 c c v c c d e l l o r t n o c # t e s e r t n e r r u c y b d n a t s p e e d v = # t e s e r s s , v 3 . 0 v = c c a / # p w c c v 3 . 0 v r o s s v 3 . 0 5 . 05a i 5 c c e d o m p e e l s c i t a m o t u a t n e r r u c , 5 v h i v = c c , v 3 . 0 v l i v = s s v 3 . 0 5 . 05a i c c a m a r g o r p d e t a r e l e c c a t n e r r u c 4 v = # e c l i v = # e o h i v h h 50 1a m v c c 5 10 3a m v l i e g a t l o v w o l t u p n i5 . 0 -8 . 0v v h i e g a t l o v h g i h t u p n ix 7 . 0v c c v c c 3 . 0 +v v d i d n a d i c i n o r t c e l e r o f e g a t l o v t c e t o r p n u r o t c e s y r a r o p m e t v c c v 0 . 3 =% 0 1 5 . 1 15 . 2 1v v h h m a r g o r p r o f e g a t l o v n o i t a r e l e c c a v c c v 0 . 3 =% 0 1 5 . 1 15 . 2 1v v l o e g a t l o v w o l t u p t u o v c c v = c c , n i m i l o a m 0 . 4 = 5 4 . 0v v 1 h o e g a t l o v h g i h t u p t u o v c c v = c c , n i m i h o a m 0 . 2 - = v x 5 8 . 0 c c v v 2 h o v c c v = c c , n i m i h o 0 0 1 - =a v c c 4 . 0 -v v o k l v w o l c c e g a t l o v t u o k c o l 4 3 . 25 . 2v notes: 1. the i cc current is listed is typically less than 2 ma/mhz with oe# at v ih . typical v cc is 3.0 v. 2. all maximum current specifications are tested with v cc = v cc max unless otherwise noted. 3. i cc active while the automatic erase or automatic program algorithm is in progress. 4. not 100% tested. 5. automatic sleep mode is enabled when addresses remain stable for t acc + 50 ns (typical).
30 r1.3/may 02 hy29lv320 0 500 1000 1500 2000 2500 3000 3500 4000 0 5 10 15 20 time in ns supply current in ma dc characteristics zero power flash figure 13. i cc1 current vs. time (showing active and automatic sleep currents) note: addresses are switching at 1 mhz. figure 14. typical i cc1 current vs. frequency note: t a = 25 c. 123456 0 2 4 6 10 frequency in mhz supply current in ma 8 2.7 v 3.6 v
31 r1.3/may 02 hy29lv320 test conditions table 15. test specifications figure 15. test setup measurement level 1.5 v output i nput 1.5 v 0.0 v 3.0 v figure 16. input waveforms and measurement levels t s e t n o i t i d n o c 0 7 - 0 8 - 0 9 - 2 1 - t i n u d a o l t u p t u oe t a g l t t 1 c ( e c n a t i c a p a c d a o l t u p t u o l )0 30 0 1f p s e m i t l l a f d n a e s i r t u p n i5s n l e v e l w o l l a n g i s t u p n i0 . 0v l e v e l h g i h l a n g i s t u p n i0 . 3v t n e m e r u s a e m g n i m i t w o l l e v e l l a n g i s 5 . 1v t n e m e r u s a e m g n i m i t h g i h l e v e l l a n g i s 5 . 1v 6.2 kohm c l 2.7 kohm + 3.3v device under test all diodes are 1n3064 or equivalent m r o f e v a w s t u p n i s t u p t u o y d a e t s l o t h m o r f g n i g n a h c h o t l m o r f g n i g n a h c d e t t i m r e p e g n a h c y n a , e r a c t ' n o dn w o n k n u e t a t s , g n i g n a h c y l p p a t o n s e o d e t a t s e c n a d e p m i h g i h s i e n i l r e t n e c ) z h g i h ( key to switching waveforms note: timing measurements are made at the reference levels specified above regardless of where the illustrations in the timing diagrams appear to indicate the measurements are made.
32 r1.3/may 02 hy29lv320 ac characteristics read operations notes: 1. not 100% tested. 2. see figure 15 and table 15 for test conditions. addresses stable t rc t acc output valid t oe t ce t oeh t oh t df ry/by# 0 v reset# outputs we# oe# ce# addresses figure 17. read operation timings r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n o i t p o d e e p s t i n u c e d e j d t s 0 7 - 0 8 - 0 9 - 2 1 - t v a v a t c r e m i t e l c y c d a e r 1 n i m0 70 80 90 2 1s n t v q v a t c c a y a l e d t u p t u o o t s s e r d d a v = # e c l i v = # e o l i x a m0 70 80 90 2 1s n t v q l e t e c y a l e d t u p t u o o t e l b a n e p i h cv = # e o l i x a m0 70 80 90 2 1s n t z q h e t f d z h g i h t u p t u o o t e l b a n e p i h c 1 x a m5 25 20 30 3s n t v q l g t e o y a l e d t u p t u o o t e l b a n e t u p t u ov = # e c l i x a m0 30 35 30 5s n t z q h g t f d z h g i h t u p t u o o t e l b a n e t u p t u o 1 x a m5 20 30 30 3s n t h e o e l b a n e t u p t u o e m i t d l o h 1 d a e rn i m0s n d n a e l g g o t g n i l l o p # a t a d n i m0 1s n t x q x a t h o # e c , s e s s e r d d a m o r f e m i t d l o h t u p t u o t s r i f s r u c c o r e v e h c i h w , # e o r o 1 n i m0s n
33 r1.3/may 02 hy29lv320 ac characteristics hardware reset (reset#) notes: 1. not 100% tested. 2. see figure 15 and table 15 for test conditions. reset timings not during automatic algorithms reset timings during automatic algorithms ry/by# 0 v t rp t ready ce#, oe# reset# t rh ry/by# t rp t ready ce#, oe# reset# t rb r e t e m a r a p n o i t p i r c s e d p u t e s t s e t n o i t p o d e e p s t i n u c e d e j d t s 0 7 - 0 8 - 0 9 - 2 1 - t y d a e r c i t a m o t u a g n i r u d ( w o l n i p # t e s e r e t i r w r o d a e r o t ) s m h t i r o g l a 1 x a m0 2s t y d a e r c i t a m o t u a g n i r u d t o n ( w o l n i p # t e s e r e t i r w r o d a e r o t ) s m h t i r o g l a 1 x a m0 0 5s n t p r h t d i w e s l u p # t e s e rn i m0 0 5s n t h r d a e r e r o f e b e m i t h g i h # t e s e r 1 n i m0 5s n t d p r e d o m y b d n a t s o t w o l # t e s e rx a m0 2s t b r e m i t y r e v o c e r # y b / y rn i m0s n figure 18. reset# timings
34 r1.3/may 02 hy29lv320 ac characteristics program and erase operations notes: 1. not 100% tested. 2. typical program and erase times assume the following conditions: 25 c, v cc = 3.0 volts, 100,000 cycles. in addition, programming typicals assume a checkerboard pattern. maximum program and erase times are under worst case condi- tions of 90 c, v cc = 2.7 volts (3.0 volts for - 70 version), 100,000 cycles. 3. excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. see table 9 for further information on command sequences. 4. excludes 0x00 programming prior to erasure. in the preprogramming step of the automatic erase algorithm, all bytes are programmed to 0x00 before erasure. 5. the typical chip programming time is considerably less than the maximum chip programming time listed since most words program faster than the maximum programming times specified. the device sets dq[5] = 1 only if the maximum word program time specified is exceeded. see write operation status section for additional information. r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 0 7 - 0 8 - 0 9 - 2 1 - t v a v a t c w e m i t e l c y c e t i r w 1 n i m0 70 80 90 2 1s n t l w v a t s a e m i t p u t e s s s e r d d an i m0 s n t x a l w t h a e m i t d l o h s s e r d d an i m5 45 45 40 5s n t t s a r o f w o l # e c r o # e o o t e m i t p u t e s s s e r d d a t s e t t i b e l g g o t n i m5 1s n t t h a r o f h g i h # e c r o # e o m o r f e m i t d l o h s s e r d d a t s e t t i b e l g g o t n i m0 s n t h p e c t s e t t i b e l g g o t r o f e m i t h g i h e l b a n e p i h cn i m0 2s n t h p e o t s e t t i b e l g g o t r o f e m i t h g i h e l b a n e t u p t u on i m0 2s n t h w v d t s d e m i t p u t e s a t a dn i m5 45 45 40 5s n t x d h w t h d e m i t d l o h a t a dn i m0 s n t l w h g t l w h g e t i r w e r o f e b e m i t y r e v o c e r d a e rn i m0 s n t l w l e t s c e m i t p u t e s # e cn i m0 s n t h e h w t h c e m i t d l o h # e cn i m0 s n t h w l w t p w h t d i w e s l u p e t i r wn i m5 35 35 30 5s n t l w h w t h p w h g i h h t d i w e s l u p e t i r wn i m0 3s n t 1 h w h w t 1 h w h w n o i t a r e p o g n i m m a r g o r p d r o w 3 , 2 , 1 p y t1 1s x a m0 0 3s n o i t a r e p o g n i m m a r g o r p p i h c 5 , 3 , 2 , 1 p y t3 2c e s x a m0 7c e s t 1 h w h w t 1 h w h w n o i t a r e p o g n i m m a r g o r p d r o w d e t a r e l e c c a 3 , 2 , 1 p y t7s x a m0 1 2s t 2 h w h w t 2 h w h w n o i t a r e p o e s a r e r o t c e s 4 , 2 , 1 p y t5 . 0c e s x a m5 . 7c e s t 3 h w h w t 3 h w h w n o i t a r e p o e s a r e p i h c 4 , 2 , 1 p y t2 3c e s e c n a r u d n e e l c y c m a r g o r p d n a e s a r e 1 n i m0 0 0 , 0 0 1s e l c y c p y t0 0 0 , 0 0 0 , 1s e l c y c t s c v v c c e m i t p u t e s 1 n i m0 5s t h h v v h h e m i t l l a f d n a e s i r 1 n i m0 5 2s n t b r # y b / y r m o r f e m i t y r e v o c e rn i m0 s n t y s u b y a l e d # y b / y r o t h g i h # e wn i m0 9s n
35 r1.3/may 02 hy29lv320 notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. figure 19. program operation timings addresses ce# t wc 0x555 pa pa pa oe# t as t ah t wph t wp t ghwl t cs we# data t ds t dh 0xa0 pd status t whwh1 ry/by# t busy t rb t vcs v cc program command sequence (last two cycles) read status data (last two cycles) d out t ch figure 20. accelerated programming voltage timings acc v hh v il or v ih t vhh t vhh v il or v ih
36 r1.3/may 02 hy29lv320 ac characteristics figure 21. sector/chip erase operation timings addresses ce# t wc 0x2aa va va sa oe# t as t ah t wph t wp t ghwl t cs t ch we# data t ds t dh 0x55 0x30 status d out t whwh2 or t whwh3 ry/by# t busy t rb t vcs v cc erase command sequence (last two cycles) read status data (last two cycles) address = 0x555 for chip erase data = 0x10 for chip erase notes: 1. sa =sector address (for sector erase), va = valid address for reading status data (see write operation status section), d out is the true data at the read address.(0xff after an erase operation). 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence.
37 r1.3/may 02 hy29lv320 ac characteristics notes: 1. va = valid address for reading toggle bits (dq[2], dq[6]) status data (see write operation status section). 2. illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle. figure 23. toggle bit timings (during automatic algorithms) t oeph t ast t busy t ch t oe t ce t rc valid status valid status valid status ry/by# dq[6], [2] we# oe# ce# addresses va va va t acc t oeh t oh t df va (second read) (first read) (stops toggling) valid data t aht t ceph t busy t ch t oe t ce t rc complement complement true valid data status data status data data valid data ry/by# dq[6:0] dq[7] we# oe# ce# addresses va va va t acc t oeh t oh t df notes: 1. va = valid address for reading data# polling status data (see write operation status section). 2. illustration shows first status cycle after command sequence, last status read cycle and array data read cycle. figure 22. data# polling timings (during automatic algorithms)
38 r1.3/may 02 hy29lv320 notes: 1. the system may use ce# or oe# to toggle dq[2] and dq[6]. dq[2] toggles only when read at an address within an erase-suspended sector. figure 24. dq[2] and dq[6] operation r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 0 7 - 0 8 - 0 9 - 2 1 - t r d i v v d i t c e t o r p n u r o t c e s y r a r o p m e t r o f e m i t n o i t i s n a r t 1 n i m0 0 5s n t p s r t c e t o r p n u r o t c e s y r a r o p m e t r o f e m i t p u t e s # t e s e rn i m4 s t t s r v d n a t c e t o r p p u o r g r o t c e s r o f e m i t p u t e s # t e s e r t c e t o r p n u r o t c e s n i m1s t t o r p e m i t t c e t o r p p u o r g r o t c e sx a m0 5 1s t r p n u e m i t t c e t o r p n u r o t c e sx a m5 1s m sector protect and unprotect, temporary sector unprotect notes: 1. not 100% tested. figure 25. temporary sector unprotect timings erase complete we# dq[6] dq[2] enter automatic erase erase erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase suspend t vidr ry/by# we# ce# reset# v id 0 or 3v t rsp t vidr 0 or 3v ac characteristics
39 r1.3/may 02 hy29lv320 note: for sector group protect, a[6] = 0, a[1] = 1, a[0] = 0. for sector unprotect, a[6] = 1, a[1] = 1, a[0] = 0. figure 26. sector group protect and sector unprotect timings ac characteristics v id v ih reset# don't care valid * valid * valid * sga, a[6], a[1], a[0] 0x60 0x60 0x40 status data ce# we# oe# t vrst t prot or t unpr sector group protect/ sector unprotect verify ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see programming and erase operations table for erase, program and endurance characterisitics. r e t e m a r a p n o i t p i r c s e d n o i t p o d e e p s t i n u c e d e j d t s 0 7 - 0 8 - 0 9 - 2 1 - t v a v a t c w e m i t e l c y c e t i r w 1 n i m0 70 80 90 2 1s n t l e v a t s a e m i t p u t e s s s e r d d an i m0 s n t x a l e t h a e m i t d l o h s s e r d d an i m5 45 45 40 5s n t h e v d t s d e m i t p u t e s a t a dn i m5 45 45 40 5s n t x d h e t h d e m i t d l o h a t a dn i m0 s n t l e h g t l e h g e t i r w e r o f e b e m i t y r e v o c e r d a e r ) w o l # e c o t h g i h # e o ( n i m0 s n t l e l w t s w e m i t p u t e s # e wn i m0 s n t h w h e t h w e m i t d l o h # e wn i m0 s n t h e l e t p c h t d i w e s l u p # e cn i m5 35 35 30 5s n t l e h e t h p c h g i h h t d i w e s l u p # e cn i m0 3s n t y s u b y a l e d # y b / y r o t h g i h # e cn i m0 9s n
40 r1.3/may 02 hy29lv320 ac characteristics 0x555 for program 0x2aa for erase pa for program sa for sector erase 0x555 for chip erase t ws t rh t wh ce# oe# addresses t wc va t as t ah we# data ry/by# t ds status d out t busy t whwh1 or t whwh2 or t whwh3 t dh 0xa0 for program 0x55 for erase pd for program 0x30 for sector erase 0x10 for chip erase reset# t cp t cph t ghel notes: 1. pa = program address, pd = program data, va = valid address for reading program or erase status (see write operation status section), d out = array data read at va. 2. illustration shows the last two cycles of the program or erase command sequence and the last status read cycle. 3. reset# shown only to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 27. alternate ce# controlled write operation timings
41 r1.3/may 02 hy29lv320 latchup characteristics notes: 1. includes all pins except v cc . test conditions: v cc = 3.0v, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions: t a = 25 o c, f = 1.0 mhz. n o i t p i r c s e d m u m i n i m m u m i x a m t i n u v o t t c e p s e r h t i w e g a t l o v t u p n i s s s n i p o / i t p e c x e s n i p l l a n o ) # t e s e r d n a # e o , ] 9 [ a , c c a / # p w g n i d u l c n i ( 0 . 1 -5 . 2 1v v o t t c e p s e r h t i w e g a t l o v t u p n i s s s n i p o / i l l a n o0 . 1 -v c c 0 . 1 +v v c c t n e r r u c0 0 1 -0 0 1a m l o b m y s r e t e m a r a p p u t e s t s e t p y t x a m t i n u c n i e c n a t i c a p a c t u p n iv n i 0 =65 . 7f p c t u o e c n a t i c a p a c t u p t u ov t u o 0 =5 . 82 1f p c 2 n i e c n a t i c a p a c n i p l o r t n o cv n i 0 =5 . 79 f p data retention r e t e m a r a p s n o i t i d n o c t s e t m u m i n i m t i n u e m i t n o i t n e t e r a t a d n r e t t a p m u m i n i m c o 0 5 10 1s r a e y c o 5 2 10 2s r a e y package drawings physical dimensions tsop48 - 48-pin thin small outline package (measurements in millimeters) 18.30 18.50 pin 1 id 11.90 12.10 0.25mm (0.0098") bsc 1.20 max 1 24 48 25 19.80 20.20 0.50 bsc 0.95 1.05 0.50 0.70 0 5 o o 0.10 0.21 0.08 0.20 0.05 0.15
42 r1.3/may 02 hy29lv320 package drawings physical dimensions fbga63 - 63-ball fine-pitch ball grid array, 7.0 x 11 mm (measurements in millimeters) note: unless otherwise specified, tolerance = 0.05

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43 r1.3/may 02 hy29lv320 ordering information hynix products are available in several speeds, packages and operating temperature ranges. the ordering part number is formed by combining a number of fields, as indicated below. refer to the ? valid combinations ? table, which lists the configurations that are planned to be supported in volume. please contact your local hynix representative or distributor to confirm current availability of specific configura- tions and to determine if additional configurations have been released. valid combinations d e e p s d n a e g a k c a p a g b f p o s t e r u t a r e p m e t s n 0 7 s n 0 8 s n 0 9 s n 0 2 1 s n 0 7 s n 0 8 s n 0 9 s n 0 2 1 s t l o v 6 . 3 - 7 . 2 : e g a t l o v g n i t a r e p o l a i c r e m m o c- -0 8 - f0 9 - f2 1 - f- -0 8 - t0 9 - t2 1 - t l a i r t s u d n ii 0 7 - fi 0 8 - fi 0 9 - fi 2 1 - fi 0 7 - ti 0 8 - ti 0 9 - ti 2 1 - t s t l o v 6 . 3 - 0 . 3 : e g a t l o v g n i t a r e p o l a i c r e m m o c0 7 - f- -- -- -0 7 - t- -- -- - note: 1. the complete part number is formed by appending the suffix shown in the table to the device number. for example, the part number for a 90 ns, industrial temperature range device in the tsop package with the top boot block option is hy29lv320tt-90i . 0 2 3 v l 9 2 y h xx-xxx s n o i t c u r t s n i l a i c e p s e g n a r e r u t a r e p m e t = k n a l b = i ) c 0 7 + o t 0 ( l a i c r e m m o c ) c 5 8 + o t 0 4 - ( l a i r t s u d n i n o i t p o d e e p s = 0 7 = 0 8 = 0 9 = 2 1 s n 0 7 s n 0 8 s n 0 9 s n 0 2 1 e p y t e g a k c a p = t = f ) p o s t ( e g a k c a p e n i l t u o l l a m s n i h t n i p - 8 4 m m 1 1 x 0 . 7 , ) a g b f ( y a r r a d i r g l l a b h c t i p - e n i f l l a b - 3 6 n o i t a c o l k c o l b t o o b = t = b n o i t p o k c o l b t o o b p o t n o i t p o k c o l b t o o b m o t t o b r e b m u n e c i v e d = 0 2 3 v l 9 2 y he s a r e r o t c e s y l n o - t l o v 3 s o m c ) 6 1 x m 2 ( t i b a g e m 2 3 y r o m e m h s a l f
44 r1.3/may 02 hy29lv320 d r o c e r n o i s i v e r . v e r e t a d s l i a t e d 0 . 11 0 / 4. e u s s i l a n i g i r o 1 . 11 0 / 7 . e d a r g e r u t a r e p m e t l a i r t s u d n i r o f v 6 . 3 - 7 . 2 o t d e g n a h c n o i t a c i f i c e p s e g a t l o v g n i t a r e p o 0 7 - v o t t n e m e r i u q r t u p n i c c a / # p w d e g n a h c h i t c e t o r p n u / t c e t o r p p u o r g r o t c e s g n i r u d. s n o i t a r e p o . a t a d i f c g n i d n o p s e r r o c d n a s r e t e m a r a p e s a r e p i h c d n a r o t c e s d e g n a h c . 9 e l b a t n i r o r r e d n a 2 2 e r u g i f d e t c e r r o c 3 . 12 0 / 5 i t i l . d e t a n i m i l e n i p c c a / # p w r o f c e p s ) t n e r r u c d a o l t u p n i ( l l a b 5 4 . 0 h t i w ) 2 m m 7 x 1 1 ( l l a b 3 6 o t r e t e m a i d l l a b 3 . 0 h t i w ) m m 5 2 . 7 x 2 1 ( l l a b 8 4 m o r f d e g n a h c c e p s e g a k c a p a g b f . y t i l i b a i l e r r e t t e b r o f r e t e m a i d memory sales and marketing division flash memory business unit hynix semiconductor inc. hynix semiconductor america inc. 10 fl., hynix youngdong building 3101 north first street 891, daechi-dong, kangnam-gu san jose, ca 95134 seoul, korea usa telephone: +82-2-3459-5980 telephone: (408) 232-8800 fax: +82-2-3459-5988 fax: (408) 232-8805 http://www.hynix.com http://www.us.hynix.com important notice ? 2001 by hynix semiconductor america. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of hynix semiconductor inc. or hynix semiconductor america (collec- tively ? hynix ? ). the information in this document is subject to change without notice. hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. devices sold by hynix are covered by warranty and patent in- demnification provisions appearing in hynix terms and condi- tions of sale only. hynix makes no warranty, express, statu- tory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. hynix makes no war- ranty of merchantability or fitness for any purpose. hynix ? s products are not authorized for use as critical compo- nents in life support devices or systems unless a specific writ- ten agreement pertaining to such intended use is executed between the customer and hynix prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

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